System-On-Chip Physical Design
This Master's course trains students to design digital CMOS integrated circuits—from high-level description to layout—using computer-aided methods that meet topological, geometric, timing, and power constraints.
Specific topics covered in the course are timing constraints and analysis; synthesis - concepts and basic flow; physical implementation (place-and-route) basic flow; clock distribution and analysis; power distribution; implementation of low power techniques; and design for testability flow.
The course has an important practical content using professional EDA tools (Cadence’s physical synthesis flow).
This course requires physical presence. Please copy this link into your browser to learn more about the application procedures for Unite! partner university students.