Digital Nanoelectronic Design

This is a Master’s course with the aim of designing digital medium-complexity CMOS integrated circuits, from hardware description to tapeout.

In this course, specific attention will be given to low-power design techniques (dynamic power reduction; clock gating; static power reduction. power gating; dynamic voltage scaling) as well as practical aspects of VLSI design (interconnects; crosstalk; robustness and variability; power supply distribution; clock distribution; buffering; input/output pads; layout and tapeout; packaging).

An introduction to test and verification will also be provided.

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This course requires physical presence. Please copy this link into your browser to learn more about the application procedures for Unite! partner university students.
https://telecos.upc.edu/en/mobility/foreign-students

University Origin (UPC) Universitat Politècnica de Catalunya
Tuition Fees https://telecos.upc.edu/en/study-programs/masters/masters-degree-in-electronic-engineering-mee?set_language=en
Course Start Date 2026-02-12
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Language Offered English
Format Physical
Field of Study Microelectronics
Course End Date 2026-06-19
End of Application Period 2025-12-01
Credits (ECTS) 5
Beginning of Application Period 2025-10-01
Academic Cycle Master's